Superb exposition! I hear the comforting
ring of clear thinking. I have just
yesterday begun my SystemC studies, with
a bet-the-farm project around my serdes
invention. Thank you millefois for your
postings. They are my first food.

A sharp concern in my proof-of-concept is
whether I can implement differential
comparators at physical ports of the FPGA.
I have registered for the AMS portion of
the 1666 group in hopes of getting a
definitive answer. I would much rather have
the diff comps on the same chip, since this
project has do demonstrate state-of-the-art
speed, combining phase modulation and
waggledance modulation for 12 bits per
cycle over 4 wires. I’m shooting for
1.2 Terabyte/second, feeding 32 channels
of 40 GbE through a 4-wire concentrator.

Best regards,
DZ